This site is an early beta and not released yet. Issues are to be expected and contents and designs are not final. Please help to test and improve it!
A note from the author: The documentation is currently in alpha and has known bugs because the content is directly parsed from the wiki without modifications. Known bugs include broken links, missing templates, a broken article order, missing pages and broken tables. These errors will be resolved before the release. Please help to test and improve it!


CPU Architecture

  • Quad-core U74 up to 1.5GHz CPU SiFive

  • Fully compliant with the RISC-V ISA specification

  • 64-bit RISC-V Application Core

  • 32KB L1 I-cache with ECC

  • 32KB L1 D-cache with ECC

  • 8 Region Physical Memory Protection

  • Virtual Memory support with up to 47 Physical Address bits

  • Integrated up to 2MB L2 Cache with ECC

  • includes RV64IMAC S7 monitor core, 16 KB L1 I-Cache with ECC, 8 KB DTIM with ECC

  • 32-bit RISC-V CPU core (E24) for real time control, support RV32IMFC RISC-V ISA

GPU Architecture

  • Imagination Technology BXE-4-32 up to 600Mhz GPU imgtech

  • Support OpenCL 3.0

  • Support OpenGL ES 3.2

  • Support Vulkan 1.2

  • Tile-based deferred rendering architecture for 3D graphics workloads, with concurrent processing of multiple tiles

  • Support for GPU visualization, up to 8 virtual GPUs

  • On fly frame buffer compression and decompression (TFBC) algorithm

  • Performance: 128 FP32 FLOPs/Clock, 256 FP16 FLOPs/Clock

System Memory

  • LPDDR4 RAM Memory Variants: 2GB, 4GB and 8GB.